UNISS-UNICA Multi-Dataflow Composer
| ID: R22 | Licence: 3-clause BSD | Owner: UNICA Contributors: UNISS | Contacts: francesca.palumbo@unica.it francesco.ratto@unica.it claudio.rubattu@uniss.it |
| Short Description | The Multi-Dataflow Composer (MDC) tool supports runtime adaptivity through the design and deployment of CGR accelerators. |
| Key features | Reconfigurability support. |
| Require | Application definition and FPGA-based System-on-Chip. |
| Provide | Ready-to-use reconfigurable HW accelerator. |
| Input | – Dataflow application specification(s) – HDL actor definition(s) – Communication protocol – Target architecture |
| Output | – RTL description of the CGR accelerator and the RTL co-processor template – Programming tables – APIs – Scripts for the VIVADO Design Environment |
| User | – SW developers that do have knowledge of HW. – HW developers that need additional features, such as AI specific accelerators. |
| Benefits for the user | – MDC generates flexible hardware accelerators. – MDC generates the drivers to delegate computation to the accelerators, masking the sw-hw communication details for AMD platforms. |
| Position in the MYRTUS DPE | Step 3 – Node Level Optimization |
| TRL@M0 | 3 (for what regards the features related to MYRTUS extensions) |
| TRL@M36 | 4-5 |
General description
MDC is an open-source design tool for the generation and management of Coarse-Grain Reconfigurable (CGR) Hardware Accelerators. The baseline tool supports multitasking through dataflow merging techniques. Input application must be specified in CAL language or ORCC IR representation. High-level synthesis tools can be integrated as external tools provided that the developer specifies the modules’ interface. A toolchain that takes as input a CNN in ONNX and includes MDC is partially integrated.
Role in the MYRTUS DPE
MDC will allow users to adopt FPGA-based Heterogeneous Multi-Processor System on Chip accelerators without the burden of generating bitstream, APIs and low level configuration files.
MYRTUS Extension/Contribution
MDC will be extended to support the design automation of multi-threaded accelerators exploiting tagged dataflow computation. The tool will also accept QONNX as input specification for the acceleration of Quantized CNN. Approximate computing will be supported through integration with Quantized NN (i.e. QONNX) and an HLS tool that supports fixed-point arithmetic (e.g. Vitis HLS). A new standalone version of the MDC tool will be made available by integrating these new features and removing dependencies from discontinued third-party components.
Plans and Expectation
Assessment Plan@M18:
Usage of the new MDC features to create the accelerators listed in R1.
Expected Results@M18:
Partial availability of the new features to be integrated in the final version of MDC with accompanied distribution material (tutorial and GitHub code).
References
- [1] University of Cagliari, University of Sassari, MDC Suite, https://github.com/mdc-suite/mdc/wiki
- [2] C. Sau, T. Fanni, C. Rubattu, L. Raffo, F. Palumbo, The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design, Microprocessors and Microsystems, 2024, https://doi.org/10.1016/j.micpro.2020.103326