UNICA, UNISS – HMPSoCs FPGA-based accelerators
| ID: R1 | Licence: 3-clause BSD |
Owner: UNICA UNISS |
Contacts: francesca.palumbo@unica.it francesco.ratto@unica.it claudio.rubattu@uniss.it |
| Short Description | HMPSoCs FPGA-based accelerators leveraging on open-source architectural templates, and exploiting coarse-grained reconfigurable (CGR) approaches for edge computation. |
| Key features | – Dataflow-based CGR coprocessors on FPGA-based MPSoCs – Multitasking: the coprocessor is reconfigured to execute a different functionality, or a different implementation of the same functionality – Multithreading: concurrent execution of multiple threads on the same accelerator – Approximate computing for AI inference, with precision reconfigurable at run time – Power and performance monitoring |
| Require | – RTL description of the CGR accelerator and the RTL co-processor template – Programming tables – APIs All these inputs are derivable with the MDC tool that is part of the MYRTUS DPE. |
| Provide | Acceleration infrastructure at the edge. |
| Input | Binary files for the CGR coprocessor (configuration bitstream), software application instrumented with the APIs to utilize the co-processing unit. |
| Output | Heterogeneous and hardware-accelerated execution of the application. |
| User | Developers of edge applications that need flexible hardware acceleration on FPGA-based MPSoCs. |
| Benefits for the user | – Higher energy efficiency than software execution, while keeping the flexibility to change functionality or implementation at run time – Accelerators derived through an automated design methodology, applicable to other dataflow-based kernels |
| Download | The tool to derive this type of accelerators is available here: github.com/mdc-suite/mdc/wiki Baseline examples of adaptive AI accelerators: github.com/mdc-suite/qonnx2mdc |
| Role in MYRTUS | Hardware-accelerated edge nodes of the MYRTUS infrastructure, on AMD Kria KV260 and Digilent ZedBoard platforms, integrated in the continuum through the Edge OS (K3s and Liqo). |
| TRL@M0 | 3 |
| TRL@M36 | To be defined |
General description
The HMPSoC accelerators are dataflow-driven, coarse-grained reconfigurable (CGR) coprocessors for FPGA-based multiprocessor systems-on-chip (MPSoCs). Starting from dataflow specifications of the functionalities to accelerate, a single reconfigurable datapath is derived that can switch among them, as shown in Figure 1. This enables:
- Multitasking, executing different tasks in an interleaved way: functional multitasking, where the accelerator is reconfigured to perform a different task, and trade-off-oriented multitasking, where it switches between different implementations of the same task according to performance or resource constraints.
- Multithreading, processing multiple instances of the same functionality concurrently, for example an encryption algorithm on a set of independent blocks, which makes better use of the customised deep pipeline of the CGR accelerator.
The same dataflow approach is also used for AI acceleration at the edge, with a streaming-based methodology that optimises execution efficiency and enables adaptivity.
Figure 1. Supported execution modes of the accelerator.
MYRTUS Extension/Contribution
Within MYRTUS, UNICA and UNISS have extended the accelerators and integrated them as edge nodes of the reference infrastructure:
- Multithreading. The multithread accelerator architecture has been defined and implemented, with example accelerators for AES encryption, FFT and HEVC filtering. On the AMD Kria KV260, the multithread architectures need fewer programmable-logic resources than replicating the accelerator for each thread, and they clearly outperform software execution on the Arm cores of the device.
- Approximate computing. For machine-learning acceleration, the precision of the computation can be reconfigured at run time, reducing power consumption with respect to full-precision computation while keeping state-of-the-art accuracy. These accelerators are derived with an automated toolchain developed in the MYRTUS DPE, and the work is now being extended towards vision transformers at the edge.
- Security. AES-128 and AES-256 encryption and decryption are supported, and a reconfigurable accelerator supporting both SHA and ASCON has been developed for crypto-agility.
- Integration in the continuum. The nodes run the Edge OS, a custom Yocto-based Linux distribution with K3s and Liqo support, within a unified design flow for deploying and orchestrating FPGA-accelerated workloads on edge MPSoCs, validated on AMD Kria KV260 and Digilent ZedBoard platforms. The nodes exchange data with the ABI gateway over HTTP, and API-based access to the Distributed Knowledge Base has been implemented.
- Monitoring. Power consumption and performance are monitored with the framework developed with UPM, described in Monitoring and Observability.
Technology Benefits and Innovations
The accelerators combine the efficiency of hardware acceleration with the flexibility usually associated with software: a single coarse-grained reconfigurable datapath can change functionality, implementation or precision at run time, and serve multiple threads concurrently, instead of requiring a dedicated accelerator for each case. Tagged-dataflow multithreading is particularly effective when workload concurrency varies and full spatial replication of the accelerator would need too many FPGA resources.
All the accelerators are derived through an automated design methodology, based on the MDC tool, that is applicable to any other dataflow-based kernel to be accelerated at the edge. Together with the Edge OS, this makes hardware-accelerated, dynamically orchestrated FPGA-based edge nodes part of a Kubernetes-based computing continuum.
Users
The primary users are hardware and embedded system designers and developers of edge applications who need energy-efficient acceleration on FPGA-based MPSoCs, while keeping the flexibility to adapt functionality, implementation or precision to changing requirements. Researchers working on reconfigurable computing and on AI acceleration at the edge can also use the open-source design flow to derive accelerators for their own dataflow-based kernels.
References
- F. Ratto, Á. P. Máinez, C. Sau et al., “An Automated Design Flow for Adaptive Neural Network Hardware Accelerators”, Journal of Signal Processing Systems, 95, 1091–1113, 2023. DOI
- F. Manca, F. Ratto, F. Palumbo, “ONNX-to-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs”, in Proc. SAMOS 2024. Zenodo
- F. Ratto, C. Rubattu, L. Raffo, F. Palumbo, “System-level Support for Multi-thread Coprocessors with Tagged-dataflow and Coarse-grained Reconfigurability on FPGA-based MPSoCs”, Journal of Systems Architecture, 2026.
- C. Rubattu, M. Fois, F. Ratto, M. Fadda, P. Ruiu, R. Delussu, L. Raffo, F. Palumbo, “Seamless Integration of FPGA-based MPSoCs into Computing Continuum Infrastructures”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2026. Zenodo
- J. Encinas et al., “Modular and Composable Framework for Multipurpose Monitoring in Heterogeneous FPGA-Based Systems”, in Proc. SAMOS 2025. Zenodo
- Target platforms: AMD Kria KV260, Digilent ZedBoard
- MDC tool: github.com/mdc-suite/mdc; github.com/mdc-suite/qonnx2mdc