TUD – dfg-mlir
| ID: R23 | Licence: ISC License | Owner: TUD | Contacts: jiahong.bi@tu-dresden.de |
| Short Description | Definition of an MLIR-based interoperability layer for the tools involved in MYRTUS DPE Node-level Optimization and Deployment. |
| Key features | – Interconnect different MLIR dialects/frameworks – Automatic optimization on execution dataflow graph – Various outputs for different hardware deployment |
| Require | – MLIR (Multi-Level Intermediate Representation). – AMD Vivado™ Design Suite. |
| Provide | – A MLIR-based tool that compiles to different hardware platforms. |
| Input | To-be-compiled kernel written in MLIR, which comes from an upper level of the DPE. |
| Output | – Ready-to-use Vitis/Vivado code/script for FPGA hardware. – Input for CGRA MLIR dialect for CGRA hardware. |
| User | – Developers. |
| Benefits for the user | Automatic optimizations and deployment. |
| Position in the MYRTUS DPE | Step 3 – Node Level Optimization and Deployment |
| TRL@M0 | 2 |
| TRL@M36 | 3-4 |
General description
The baseline of this results consists of independent dialects in MLIR (e.g., for simple dataflow graphs, and ML operators) and existing tools (e.g., CGRA compiler toolchains) with no integration in MLIR. Some MLIR dialects are rather mature (e.g., linalg) and others less so. In the baseline there is no integrated solution and key dialects and dialect extensions are missing to implement the planned functionality of the DPE.
Role in the MYRTUS DPE
dfg-mlir serves as a part of the interoperability layer in the DPE Node-Level Optimization and Deployment step. It accepts input from higher abstraction level code (e.g. linalg) and generates codes targeting different hardware acceleration platforms (i.e. FPGA and CGRA). In this MLIR-based framework, optimizations on the execution dataflow graph will be applied to achieve better performance.
MYRTUS Extension/Contribution
This is a new result, consistent with the seamless integration of node-level tools. The interoperability layer will enable a seamless programming and exploration flow, not possible today due to fragmented toolchains.
Plans and Expectation
Assessment Plan@M18:
Initial bilateral or trilateral interoperability between tools demonstrated in a small testbed. An example would be an external DSL integrated via MLIR into a mock application graph, with partially automatic code generation for a platform with RISC-V and a CGRA/FPGA.
Expected Results@M18:
Interoperability of other tools in DPE, such as FPGA backend or CGRA tools.