TUD – Mocasin: rapid prototyping framework for mapping software applications onto heterogeneous MPSoC platforms
| ID: R19 | Licence: ISC licence |
Owner: TUD |
Contacts: robert.khasanov@tu-dresden.de |
| Short Description | Mocasin is an open-source, rapid prototyping framework for exploring and evaluating mapping strategies for parallel dataflow applications on heterogeneous platforms. |
| Key features | – Support for different Models of Computation (MoCs) and input formats. – Models heterogeneous platforms and their communication structure. – Provides heuristic and metaheuristic mapping strategies for design space exploration. – Explores Pareto-optimal mappings under multiple objectives (e.g., execution time and energy). – Simulates mapped applications using execution profiles and traces. – Enables rapid prototyping in Python. |
| Require | – Python 3.11+. – SimPy 4.1.2. – MPsym 0.6.2. |
| Provide | A high-level prototyping framework for mapping and evaluation of dataflow applications onto multi-processor platforms. |
| Input | – Application description in Mocasin’s native YAML format: the dataflow graph (processes and channels) exported by PICEA, annotated with execution profiles for each processing element type. – Platform model of the target node (e.g., Kria KV260, RISC-V+CGRA edge node). |
| Output | – Pareto-optimal operating points (mappings annotated with non-functional characteristics), exported as a mapping table and intended as input to the MIRTO Cognitive Engine. – Simulated execution time and execution traces of the mapped application. |
| User | Developers. |
| Benefits for the user | Automatic design space exploration. |
| Download | github.com/tud-ccc/mocasin |
| Position in the MYRTUS DPE | Step 3 – Node-Level Optimization and Deployment. |
| TRL@M0 | 2-3 |
| TRL@M36 | 4-5 |
General description
Mocasin is a research framework for design space exploration of dataflow applications, such as task graphs, Kahn Process Networks, and Synchronous Data Flow, on heterogeneous multi-core platforms modeled in terms of processing elements and their communication resources. Mocasin provides heuristic and metaheuristic mapping strategies to explore how application processes can be assigned to processing elements, and uses execution profiles and traces to simulate and evaluate the mappings [1].
Role in the MYRTUS DPE
Mocasin enables design space exploration of dataflow applications on the AMD Kria KV260 and the RISC-V+CGRA edge node. It takes the application topology exported by PICEA, combined with execution profiles of each process on the available processing elements, and evaluates alternative mappings of application processes to processing elements, helping assess implementation options for these heterogeneous targets. The resulting Pareto-optimal operating points, each of which also determines which implementation executes each process, are intended to feed the MIRTO Cognitive Engine.
MYRTUS Extension/Contribution
Within the MYRTUS project, Mocasin was extended in the following areas:
- Platform models for the Kria KV260 (CPU cores and an FPGA accelerator) and the multi-core RISC-V+CGRA edge node (RISC-V cores and CGRA accelerators connected through a network-on-chip).
- Heterogeneity-aware mapping that respects process-to-PE eligibility constraints, integrated into the built-in heuristic and metaheuristic mappers.
- A native YAML input format for describing application topology and execution behavior, in which each process can be described as a Synchronous Data Flow (SDF) actor or a Kahn Process Network (KPN) process, so that both can be mixed in one application.
Separately, the PICEA compilation flow was extended to export application topology in the YAML format. Combined with execution profiles, the exported description serves as input to Mocasin’s simulation and design space exploration workflow. Execution profiles are collected from Vitis HLS reports (or, as a preliminary estimate, from LAKSA) for the FPGA, and from measurements on the target processor for the CPU.
Technology Benefits and Innovations
Mocasin provides an abstraction-based environment for exploring and evaluating alternative mappings of dataflow applications onto heterogeneous platforms. Researchers can assess candidate mappings through high-level, trace-based simulation before committing to target-specific implementations. Because it simulates computation and communication events at a higher abstraction level than instruction-level simulators, it shortens the design and evaluation time of hardware platforms and applications. As an open-source, modular framework, it can be extended with new mapping algorithms, allowing researchers to prototype and test their ideas within a common environment.
Users
Mocasin is intended primarily for researchers and developers working on dataflow applications, heterogeneous architectures, and mapping or scheduling algorithms.
Application Domains
Mocasin targets dataflow applications mapped onto heterogeneous platforms. Its modular architecture supports different models of computation, platform configurations, and mapping strategies. Within MYRTUS, Mocasin is used to explore mappings for heterogeneous platforms with FPGA and CGRA accelerators, generating mapping candidates for adaptive reconfigurable execution. Before MYRTUS, research using Mocasin explored heuristic and metaheuristic mapping strategies, mapping representations, symmetry-aware design space exploration, hybrid design-time/runtime mapping, multi-application resource management, and robust mapping using bio-inspired design centering.
References
- [1] C. Menard, A. Goens, G. Hempel, R. Khasanov, J. Robledo, F. Teweleitt, J. Castrillon, “Mocasin—Rapid Prototyping of Rapid Prototyping Tools: A Framework for Exploring New Approaches in Mapping Software to Heterogeneous Multi-cores”, in DroneSE and RAPIDO 2021: System Engineering for constrained embedded systems, ACM, 2021, pp. 66–73. doi: 10.1145/3444950.3447285
- [2] Mocasin: github.com/tud-ccc/mocasin