LAKSA

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TUD – LAKSA: Linear Algebra Kernel Streaming Architecture

ID: R26 Licence:
GPLv3		 Owner:
TUD		 Contacts:
jiahong.bi@tu-dresden.de
Short DescriptionAn MLIR-based compiler for automated, resource-aware FPGA accelerator generation.
Key features– Automatic analysis and classification of MLIR linalg kernels.
– Generation of memory-efficient streaming dataflow architectures with line buffers.
– Hardware-aware Design Space Exploration under constraints of BRAM and DSP.
– Automatic loop optimization, HLS pragma insertion, and FIFO buffer sizing.
Require– MLIR (Multi-Level Intermediate Representation).
– AMD Vitis™ HLS and Vivado™ Design Suite.
– Gurobi ILP Solver.
ProvideAutomated, hardware-aware FPGA compilation and optimization.
InputKernels expressed as MLIR linalg.generic operations, coming either from quantized CNN models imported through IREE or from DSP applications described through the filter and base2 dialects.
OutputReady-to-use Vitis HLS C++ code and Vivado scripts for FPGA hardware, together with the files needed to run the generated accelerator through the companion Linux driver.
UserDevelopers.
Benefits for the userAutomated hardware optimization and deployment with reduced development effort.
Downloadgithub.com/tud-ccc/laksa
Position in the MYRTUS DPEStep 3 – Node-Level Optimization and Deployment.
TRL@M02-3
TRL@M366-7

General description

LAKSA (Linear Algebra Kernel Streaming Architecture) is an MLIR-based higher-level synthesis compiler that automatically generates optimized FPGA accelerators from high-level computational kernels, without any user-provided pragmas, templates or optimization directives. Targeting resource-constrained edge FPGAs, it combines memory-efficient streaming architectures with hardware-aware design space exploration to optimize performance within the available BRAM and DSP budgets. The compiler provides an automated workflow from MLIR representations to FPGA hardware implementation [1, 2].

Role in the MYRTUS DPE

LAKSA provides an HLS-based general FPGA compilation flow within Step 3 of the MYRTUS DPE, as one of the backends of the PICEA compilation framework, alongside the MDC and CGRA toolflows. It accepts computational kernels represented as MLIR linalg.generic operations from the DPE frontends, that is, machine learning models imported through IREE and DSP applications described through the filter and base2 dialects, and connects them to the vendor HLS/FPGA toolchain. A companion Linux driver [3], tested on AMD Kria KV260 hardware, supports the execution of the generated accelerators through DMA and AXI-Lite interfaces. The estimates produced by LAKSA are also used by Mocasin to explore, at node level, which parts of the application run on the CPU and which on the FPGA.

MYRTUS Extension/Contribution

Developed within MYRTUS, LAKSA introduces an MLIR-based compiler infrastructure for general-purpose FPGA acceleration. LAKSA reimplements the DFG dialect from dfg-mlir [4] to represent dataflow processes and FIFO channels. Its compiler passes analyze computational kernels and construct memory-efficient streaming architectures [2].

To address the resource constraints of edge FPGAs, LAKSA introduces an ILP-based DSE that jointly models BRAM and DSP utilization to determine suitable parallelization and resource configurations, which are finally inserted as HLS pragmas. The compiler also incorporates automatic FIFO sizing based on the estimated execution cycles of each DFG node, without the need to run HLS repeatedly. The compiler introduces a new dialect, emithls, which is used to represent the HLS-specific constructs and bridges the IR and code generation.

The implementation provides an automated compilation and deployment workflow, including HLS code generation, hardware implementation scripts, and programs compatible with the Linux driver [3]. The compiler has been validated on different kernels against several state-of-the-art works, showing a better tradeoff between performance and resource utilization [2].

Technology Benefits and Innovations

LAKSA addresses the challenges of FPGA programming by combining automated compilation with hardware-aware optimization. Its automatic line-buffer optimization reduces on-chip memory requirements, while joint BRAM and DSP resource modeling enables efficient parallelization on resource-constrained edge FPGAs. Compared with existing frameworks, LAKSA improves design automation and resource scalability. In the evaluation reported in [2], it outperforms the MLIR-based framework StreamHLS when the DSP budget is restricted, and delivers faster end-to-end CNN inference than FINN, while respecting the given resource constraints in all cases.

Users

LAKSA targets application developers seeking FPGA acceleration for computationally intensive workloads, as well as compiler engineers integrating FPGA support into MLIR-based toolchains.

Application Domains

LAKSA primarily targets edge AI and machine learning inference, particularly workloads involving convolutional neural networks. Its evaluated applications include convolutional layers, depthwise-separable convolutions, residual blocks, fully connected layers and LeNet-5, covering computational patterns commonly found in image processing and computer vision [2]. LAKSA is applicable to both MYRTUS use cases: Mobility, which involves computational patterns supported by the compiler, and Healthcare, which requires acceleration of finite impulse response (FIR) filters that can be expressed as convolution kernels.

References

Competenze

Postato il

11 Novembre 2026